Established 1992 in Silicon Valley. Comit provides complete chip, board and software engineering services to customers worldwide.
PROCESS TOOLS
- Fiesta® CACT
- Fiesta® CWGT
- Fiesta® CRST
- Fiesta® CSMT
- Fiesta® CVXT
- Fiesta® CMMT
- Fiesta® CSGT
- Fiesta® CMBT
IP CORES
MODELS
FiestaŽ Process Tools

Comit's FiestaŽ is an integrated set of tools with a vision to painlessly transform specifications to product, by producing as much of code and documentation automatically as possible, and simultaneously setting up a compatible verification environment from the start. Designers, therefore, are free to focus on designing state machines and creating tests. Coexists with industry standard EDA tools for simulation, synthesis and layout.

The FiestaŽ toolkit addresses key design issues such as Design Entry, Change Management, Design Verification to get your designs up and running early with a high confidence level.

FiestaŽ Installation Modes: Standalone Mode

The following FiestaŽ process Acceleration Tools can be purchased and used in standalone mode:

 
FiestaŽ CACT Architecture capture Tool

Accepts block level architectural input including third party IP and generates implementation roadmap by defining placeholders for all modules and interfaces


  FiestaŽ CWGT Waveform & Constraints Generation Tool

Produces output signal waveforms based on a GUI based input of signals and their transitions


  FiestaŽ CRST Register Specification Tool

Accepts register bank definitions for a chip. Generates and regenerates documentation, software interface definitions, hardware implementations and verification definitions, preserving consistency, and avoiding errors


  FiestaŽ CSMT Finite State Machine Editor

Generates synthesizable Verilog code, and diagrams for documentation from state machines


  FiestaŽ CVXT Open Verification Environment

Provides the ability to build parallel, automated, synchronized, self-checking verification testbenches for complex ASIC, SoC and programmable SoC designs. The environment bolts on to industry standard Verilog simulators and supports both real-world system testing and rigorous hardware module level and interface tests.


  FiestaŽ CMMT Simulation Memory Modeler

Generates dynamically configurable simulation time memory models that can be used in advanced system-level verification


  FiestaŽ CSGT Synthesis Script Generation Tool

Accepts constraints and generates script to automate synthesis flow for popular synthesis tools


  FiestaŽ CMBT Memory BIST Controller

Memory BIST controller with full-speed testing and automatic fuse-map generartion for laser repair stations


  FiestaŽ CAVT AHDL to VHDL Conversion tool

Converts Altera's proprietary HDL - AHDL to portable VHDL files to target any technology


Integrated Toolkit Mode

The FiestaŽ Process Standardization & Acceleration Toolkit is also available as a set of integrated tools where the output of one tool forms the input of another tool in the chain. Click here for an
Overview of the Integrated Fiesta Process Standardization & Acceleration Toolkit.
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