Established 1992 in Silicon Valley. Comit provides complete chip, board and software engineering services to customers worldwide.
PROCESS TOOLS
- Fiesta® CACT
- Fiesta® CWGT
- Fiesta® CRST
- Fiesta® CSMT
- Fiesta® CVXT
- Fiesta® CMMT
- Fiesta® CSGT
- Fiesta® CMBT
IP CORES
MODELS
FiestaŽ CMMT Simulation Memory Modeler

 Benefits
 Key Features
 Specifications
 Environment



FiestaŽ CMMT is a tool to generate simulation time memory models that can be used in advanced system-level verification. FiestaŽ CMMT can generate memories with built-in high-level task-definitions to facilitate access from the Comit FiestaŽ CVXT Open Verification Environment or standalone Tcl test cases to set up and read data in blocks.

FiestaŽ CMMT can configure memory models to any size. Width and depth are dynamically changeable at run time. Memory models generated can be used in test environments involving many interfaces like Ethernet, Voice (SCC), ADSL, HPNA, USB and their peripheral models in a test environment.

Benefits
  • Easily set up and test interfaces needing large packet transfers
  • Automatically compare transmit and receive data with easy PLI access
  • Easily detect faults in compared data and debug interfaces
  • Shorten verification cycles
Key Features
  • Direct instantiation in the verification environment with different memory names
  • Depth and width specification using PLI
  • Initialization to desired values using PLI
  • Maximum memory area limited only by simulator memory
  • Can be used in Verilog and Tcl environments
  • Memory can be read / written with simple commands (PLI), for example:


  • $cmread (memory_name,
    address_to_be_read_from ,
    register_to_be_stored_in )
    $cmwrite (memory_name,
    address_to_be_writen_to, data_reg)

Specifications

Inputs/Outputs
  • Test bench (Comit FiestaŽ CVXT or other Verilog/Tcl environment)

Environment

Verilog, Tcl, C


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