Established 1992 in Silicon Valley. Comit provides complete chip, board and software engineering services to customers worldwide.
- Fiesta® CACT
- Fiesta® CWGT
- Fiesta® CRST
- Fiesta® CSMT
- Fiesta® CVXT
- Fiesta® CMMT
- Fiesta® CSGT
- Fiesta® CMBT
FiestaŽ CVXT Open Verification Environment

 Key Features

FiestaŽ CVXT is a complete Open Verification Environment. It saves time by allowing rapid and painless implementation of module-interactive system level testing that is difficult to do in Verilog or C. Commonly available alternatives for system level verification require the designer to master an additional or proprietary syntax or language. In FiestaŽ CVXT, tests are specified in Tcl using a set of just 12 commands. The CVXT Verification Engine provides the needed interactivity between tests and models to simulate a real-world environment.

FiestaŽ CVXT offers the ability to build parallel, automated, synchronized self-checking verification testbenches for complex ASIC, SoC and programmable SoC designs. The environment bolts on to industry standard Verilog simulators and supports both real-world system testing and rigorous hardware module level and interface tests. The user can either run system level code intended for final silicon to test functionality, or do feature-by-feature self-checking of the chip modules, in parallel and in simultaneous interaction with other modules in the design

A library of Models of popular interfaces, peripherals and storage elements is available to jump-start the SoC verification effort.

  • Easy adoption due to open Tcl based environment
  • Speeds up verification by automating real-world fully parallel testing
  • Multiple test modes allows easy verification of design intent or rigorous checking of modules and interfaces
  • Speedy testing of different prototypes provide rapid feedback for architecture adjustments
  • Quickly tests different embedded processors by changing testchips and Bus Functional Models (BFM)
  • Highly automated environment makes it convenient to run self-checking tests
  • Completely scripted - requires no recompilation or elaboration, allowing for rapid changes
Key Features
  • Sophisticated Verification Engine connects Verification Workbench to user-defined testbenches
    • Uses existing Verilog/C models
    • Supports industry standard Verilog simulators
    • Tests accuracy of modules and interfaces at the RTL level
    • Synchronizes tests with each other and with the simulator
    • Runs test in parallel and in simultaneous interaction with other modules in the design
    • Supports infinite number of parallel tests with independent execution contexts
    • Supports feature-by-feature self checking of modules
    • Supports if-then-else, events and triggers
    • Automatically waits for events and triggers from other interfaces
    • Supports top-down test-my-chip or bottom-up check-all- modules-and-interfaces mode
    • Supports execution of system level code to check functional intent
    • Observes and logs results
  • DUT Socket architecture enables easy testing of multiple prototypes
  • Testchip Socket enables plugging in of embedded processor testchips
  • Wrapper architecture supports integration of user defined and third party BFM and peripheral models from expandable model library
  • Model library supports BFM and peripheral models


  • DUT Verilog code
  • BFMs, PMs and memory models: Verilog, C
  • Tests: tcl
  • Top level control: tcl
  • Test logs; Test results: .LOG, .RPT


OS Version Simulator Version
Solaris (sparc) 2.7 / 2.8 (7/8) nc-Verilog 3.2/3.3/3.4
Redhat Linux 7.1 / 7.2 modelsim 5.6

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