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DDR1 & DDR2 SDRAM Controller Core IP



The Comit DDR1 & DDR2 SDRAM Controller is available in synthesizable RTL and/or netlist format. The core is capable of delivering upto full 333MHz/667Mbps data rate performance per pin in 0.13 micron ASIC implementation, depending on options selected. It supports up to 4Gb DDR1/DDR2 memory devices, with either 4 or 8 banks, from major vendors, and can be customized for various microprocessor bus or specific application bus interfaces, speed grades, FPGA/ASIC vendors, and, of course, end-user applications



The Core adheres to JEDEC standards, comes with a generic application bus interface, and supports multiple agents. It supports multiple inbuilt arbitration schemes (RR, Weighted RR), and will accept user defined external arbitration schemes. Programmable CAS latency and configurable address mapping enables bandwidth optimization. Configurable command queue depth optimizes bank activation, pre-charge and data rate.

The core supports programmable timing parameters, programmable auto refresh time interval, and supports power-down and self refresh. It supports DLL based DDR data (DQ/DQS) interface, and provides enable/disable support for on-die termination. The core generates manufacturer / device dependent timing parameter files for register programming as well.

Download Datasheet

A 2 page datasheet is available for your review.
Click here to download the datasheet.

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